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Data Sheet No. PD60230 revAa
PFC ONE CYCLE CONTROL PFC IC
Features
* * * * * * * * * PFC with IR proprietary "One Cycle Control" Continuous conduction mode (CCM) boost type PFC No line voltage sense required Programmable switching frequency (50kHz-200kHz) Programmable output overvoltage protection Brownout and output undervoltage protection Cycle-by-cycle peak current limit Soft start User initiated micropower "Sleep Mode" * * * * * * * * * * Open loop protection Maximum duty cycle limit of 98% User programmable fixed frequency operation Min. off time of 150-350ns over freq range VCC under voltage lockout Internally clamped 13V gate drive Fast 1.5A peak gate drive Micropower startup (<200 A) Latch immunity and ESD protection Parts also available Lead-Free
IR1150S(PbF) IR1150IS(PbF)
Description
The PFC IR1150 is a power factor correction (PFC) control IC designed to operate in continuous conduction mode (CCM) over a wide range input line voltages. The IR1150 is based on IR's proprietary "One Cycle Control" (OCC) technique providing a cost effective solution for PFC. The proprietary control method allows major reductions in component count, PCB area and design time while delivering the same high system performance as traditional solutions. The IC is fully protected and eliminates the often noise sensitive line voltage sensing requirements of existing solutions. The IR1150 features include programmable switching frequency, programmable dedicated 8-Lead SOIC over voltage protection, soft start, cycle-by-cycle peak current limit, brownout, open loop, UVLO and micropower startup current. In addition, for low standby power requirements (Energy Star, 1W Standby, Blue Angel, etc.), the IC can be driven into sleep mode with total current consumption below 200A, by pulling the OVP pin below 0.62V.
Package
IR1150 Application Diagram
V OUT
AC LI NE
-
+
BRIDGE
AC NEUTRAL 1 2 3 4
V cc
IR1150 COM FREQ ISNS OVP GATE VCC VFB COMP 8 7 6 5 +
+
RTN
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IR1150S/IR1150IS(PbF)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltages are absolute voltages referenced to COM. Thermal resistance and power dissipation are measured under board mounted and still air conditions.
Parameters
VCC voltage Freq. voltage ISNS voltage VFB voltage COMP voltage Gate voltage Continuous gate current Max peak gate current Junction temperature Storage temperature Thermal resistance Package power dissipation ESD protection
Symbols
V CC VFREQ. VISNS V FB VCOMP VGATE IGATE IGATEPK TJ TS RJA PD VESD
Min.
-0.3 -0.3 -10 -0.3 -0.3 -0.3 -5 -1.5 -40 -55 -- -- --
Max.
22 10.5 3 10.5 10 18 5 1.5 150 150 128 675 2
Units Remarks
V V V V V V mA A
oC oC
Not internally clamped
C/W mW kV
SOIC-8 SOIC-8 TAMB = 25oC Human body model*
Recommended Operating Conditions
Recommended operating conditions for reliable operation with margin
Parameters
Supply voltage Junction temperature Ambient temperature Ambient temperature Switching frequency
Symbols
V CC TJ TA TA FSW
Min. Typ.
15 -25 0 -25 50 18 -- -- -- --
Max.
20 125 70 85 200
Units
V C C C kHz
Remarks
IR1150S IR1150IS
Electrical Characteristics
The electrical characteristics involve the spread of values guaranteed within the specified supply voltage and junction temperature range TJ from - 25 C to 125C. Typical values represent the median values, which are related to 25C. If not otherwise stated, a supply voltage of VCC =15V is assumed for test condition
Supply Section
Parameters
Symbols
VCC ON VCC UVLO VCC HYST
Min. Typ.
12.2 10.2 1.8 12.7 10.7 --
Max.
13.2 11.2 2.2
Units
V V V
Remarks
VCC turn-on threshold VCC turn-off threshold (under voltage lock out) VCC turn-off hysteresis
*Per EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5K series resistor)
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IR1150S/IR1150IS(PbF)
The electrical characteristics involve the spread of values guaranteed within the specified supply voltage and junction temperature range TJ from - 25 C to 125C. Typical values represent the median values, which are related to 25C. If not otherwise stated, a supply voltage of VCC =15V is assumed for test condition.
Electrical Characteristics cont.
Parameters
Operating current
Symbols
ICC
Min. Typ.
-- -- -- 18 36 8 -- 125 0.615
Max.
22 40 10 175 200 0.665
Units
mA mA mA uA uA
V
Remarks
CLOAD=1nF fSW=200kHZ CLOAD=10nF fSW=200kHZ Standby mode - inactive gate Internal oscillator running VCC =V CC ON -0.1V VOVP<0.5V (typ),VCC =15V VCC =15V
Startup current Sleep current Sleep mode threshold
ICCSTART ISLEEP VSLEEP
-- -- 0.565
Oscillator Section
Parameters
Switching frequency Initial accuracy Voltage stability Temperature stability Total variation Long term stability Maximum duty cycle Minimum duty cycle Minimum off time
Symbols
f SW fSW ACC VSTAB TSTAB fVT FSTABLT DMAX DMIN Toffmin
Min. Typ.
50 -- -- -- -- -- 93 -- 200 -- -- 0.2 2 10 0.1 -- -- 300
Max.
200 5 3 -- -- 0.5 98 0 400
Units
kHz % % % % % % % ns
Remarks
RSET = 165k -37k approx. TA = 25oC 13V Protection Section
Parameters
Open loop protection (OLP) Vfb threshold Output under voltage protection (OUV) Output over voltage protection (OVP) OVP hysteresis Peak current limit protection (IPKLMT) ISNS voltage threshold VOUV VOVP -- VISNS 49 104 350 -1.11 51 105.5 450 -1.04 53 107 550 -0.96 %VREF %VREF mV V Brown out protection VOLP 17 19 21 %VREF
Symbols
Min. Typ.
Max.
Units
Remarks
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IR1150S/IR1150IS(PbF)
Internal Voltage Reference Section
Parameters
Reference voltage Line regulation Temp stability Total variation
Symbols
V REF RREG TSTAB VTOT
Min. Typ.
6.9 -- -- 6.8 7.0 12 0.4 --
Max.
7.1 25 -- 7.1
Units
V mV % V
Remarks
TA = 25oC 13.5V Voltage Error Amplifier Section
Parameters
Transconductance Source/sink current IOVEA Soft start delay time (calculated) VCOMP voltage (fault) Effective VCOMP voltage Input bias current Open loop bandwidth Input offset voltage temp coefficient Common mode rejection ratio Output low voltage Output high voltage VCOMP start voltage VCOMP FLT VCOMP EFF IIB BW TCIOV CMRR VOL V OH VCOMP START -- -- -- -- -- 5.71 300 -- 1.2 6.05 -0.2 1 -- 100 -- 6.15 500 -0.5 -- 10 -- 0.5 6.8 700 1.5 0.2 V V V A MHz V/oC dB V V mV VFB=0V, -25oC TAMB125oC t ss
Symbols
gm
Min. Typ.
30 30 20 -- 40
Max.
55 65 90 --
Units
S A A ms
Remarks -25oC TAMB125oC
TAMB = 25oC -25oC TAMB125oC RGAIN=1k, CZERO=0.33F CPOLE=0.01F, fXO=28Hz @ 1mA (max) initial @ 25A steady state
40
45 40
Current Amplifier Section
Parameters
DC gain Corner frequency Input offset voltage ISNS bias current Input offset voltage temp coefficient Common mode rejection ratio Blanking time
Symbols
g DC fC V IO IB TCIOV CMRR TBLANK
Min. Typ.
-- 200 -- -- -- -- 230 150 2.5 -- 1 200 -- 100 350
Max.
-- 280 4 300 10 -- 450 600
Units
V/V kHz mV A V/oC dB ns ns
Remarks
VFB=0V,-25oC TAMB125oC
TAMB = 25oC -25oC TAMB125oC
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IR1150S/IR1150IS(PbF)
Gate Driver Section
Parameters
Gate low voltage Gate high voltage Gate high voltage Rise time Fall time Out peak current Gate voltage @ fault
Symbols
VGLO VGTH VGTH tr tf IOPK VG fault
Min. Typ.
-- -- 9.5 -- -- -- -- 1.5 -- 1.2 13 -- 20 70 20 70 -- --
Max.
1.5 18 -- -- -- -- -- -- 1.8
Units
V V V ns ns ns ns A V
Remarks
IGATE=200mA V CC =20V VCC =11.5V CLOAD = 1nF, VCC=16V CLOAD = 10nF, VCC=16V CLOAD = 1nF, VCC=16V CLOAD = 10nF, VCC=16V CLOAD = 10nF, VCC=16V IGATE=20mA
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IR1150S/IR1150IS(PbF)
Block Diagram
BIAS & REFERENCES
UVLO
7
VCC
SLEEP
0.5V
OVP/EN 4
1.055VREF
CLOCK
2
FREQ
1.0V
I SNS 3 +
Vm VREF
MAX DUTY CYCLE LIMIT
S R
Q Q
FAULT
VFB COMP
8
6 5
FAULT RESET
GATE
1
COM
FAULT PROTECTION
OPEN LOOP PROTECTION OUTPUT UNDER VOLTAGE FAULT
Lead Assignments & Definitions
Lead Assignment IR1150S 2
COM FREQ I SNS 1 2 3 8 7 6 GATE
Pin# 1
Symbol COM FREQ I SNS OVP/EN COMP VFB VCC GATE
Description Ground Frequency Set Current Sense Overvoltage Fault Detect / Enable Voltage Loop Compensation Output Voltage Sense IC Supply Voltage Gate Drive Output
3
V CC VFB COMP
4 5 6 7 8
OVP/EN
4 8 LEAD SOIC
5
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IR1150S/IR1150IS(PbF)
General Description
The PFC IR1150 is intended for boost converters for power factor correction operating at a fixed frequency in continuous conduction mode. The IC operates with two loops; an inner current loop and an outer voltage loop. The inner current loop is fast, reliable and does not require sensing of the input voltage in order to create a current reference. This inner current loop sustains the sinusoidal profile of the average input current based on the dependency of the pulse width modulator duty cycle on the input line voltage in order to determine the analogous input line current. Thus, the current loop uses the embedded input voltage signal to control the average input current to follow the input voltage. The IR1150 enables excellent THD performance. In light load conditions, a small distortion occurs at zerocrossing due to the finite boost inductance but this is negligible and well within EN61000-3-2 Class D specifications. The outer voltage loop controls the DC bus voltage. This voltage is fed into the voltage error amplifier to control the slope of the integrator ramp and sets the amplitude of the average input current. The two loops combine to control the amplitude, phase and shape of the input current, with respect to the input voltage, giving near-unity power factor. The IC is designed for robust operation and provides protection from system level over current, over voltage, under voltage, and brownout conditions.
IC Supply
The UVLO circuit monitors the VCC pin and maintains the gate drive signal inactive until the VCC pin voltage reaches the UVLO turn on threshold, (VCC ON). As soon as the VCC voltage exceeds this threshold, provided that the VFB pin voltage is greater than 20%VREF, the gate drive will begin switching (under Soft Start) and increase the pulse width to its maximum value as demanded by the output voltage error amplifier. If the voltage on the VCC pin falls below the UVLO turn off threshold, (VCC UVLO), the IC turns off, gate drive is terminated, and the turn on threshold must again be exceeded in order to re-start the process and move into Soft Start mode.
Soft Start
Soft Start controls the rate of rise of the output voltage error amplifier in order to obtain a linear control of the increasing duty cycle as a function of time. The Soft Start time is controlled by voltage error amplifier compensation components selected, and is user programmable based on desired loop crossover frequency.
Frequency Select
The switching frequency of the IC is programmable by an external resistor at the FREQ pin. The design incorporates min/max restrictions such that the minimum and maximum operating frequency fall within the range of 50-200kHz.
Gate Drive
The gate drive is a totem pole driver with 1.5A capability. If higher currents are required, additional external drivers can be used.
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IR1150S/IR1150IS(PbF)
Detailed Pin Description
COM: Ground
This is the ground potential pin of the integrated control circuit. All internal devices are referenced to this point. The output voltage of the boost converter is sensed via a resistive divider and fed into this pin, which is the inverting input of the output voltage error amplifier. The impedance of the divider string must be low enough so as to not introduce substantial error due to the input bias currents of the amplifier, yet high enough so as to minimize power dissipation. A typical value of external divider impedance is 1M. The error amplifier is a transconductance type which yields high output impedance, thus increasing the noise immunity of the error amplifier output. This also eliminates input divider string interaction with compensation feedback capacitors and reducing the loading of divider string due to a low impedance output of the amplifier. This pin is the inverting Current Sense Input & Peak Current Limit. The voltage at this pin is the negative voltage drop, sensed across the system current sense resistor, representing the inductor current. This voltage is fed into the Peak Current Limit protection comparator with threshold arond -1V. This protection circuit incorporates a leading edge blanking circuit following the comparator to improve noise immunity of the protection process. The current sense signal is also fed into the current sense amplifier. The signal is amplified, filtered of high frequency noise and then injected into a summing node where it is subtracted from the compensation voltage VCOMP. The signal on this pin must be previously filtered with an RC cell to provide additional noise immunity. The input impedance of this pin is 5k.
ISNS: Current Sense input
VFB: Output Voltage Feedback
VCC: Supply Voltage
COMP: Voltage Loop Compensation
External circuitry from this pin to ground compensates the system voltage loop and soft start time. This is the output of the voltage error amplifier. This pin will be discharged via internal resistance when a fault mode occurs.
GATE: Gate Drive Output
This is the gate drive output of the IC. Drive voltage is internally limited and provides 1.5A peak with matched rise and fall times.
This is the supply voltage pin of the IC and it is monitored by the under voltage lockout circuit. It is possible to turn off the IC by pulling this pin below the minimum turn off threshold voltage, without damage to the IC. To prevent noise problems, a bypass ceramic capacitor connected to VCC and COM should be placed as close as possible to the IR1150S. This pin is not internally clamped, therefore damage will occur if the maximum voltage is exceeded.
OVP/EN: Over Voltage Protection / Enable
This pin is the input to the over voltage protection comparator the threshold of which is internally programmed to 105.5% of VREF. A resistive divider feeds this pin from the output voltage to COM and inhibits the gate drive whenever the threshold is exceeded. Normal operation resumes when the voltage level on this pin decreases to below the pin threshold. This pin is also used to activate "sleep" mode by pulling the voltage level below 0.62V (typ).
FREQ: Frequency Set
This is the user programmable frequency pin. An external resistor from this pin to the COM pin programs the frequency. The operational switching frequency range for the device is 50kHz - 200kHz.
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IR1150S/IR1150IS(PbF)
Operating States
UVLO Mode
The IC remains in the UVLO condition until the voltage on the VCC pin exceeds the VCC turn on threshold voltage, VCC ON. During the time the IC remains in the UVLO state, the gate drive circuit is inactive and the IC draws a quiescent current of ICC START. The UVLO mode is accessible from any other state of operation whenever the IC supply voltage condition of VCC < VCC UVLO occurs.
Normal Mode
The IC enters normal operating mode once the soft start transition has been completed. At this point the gate drive is switching and the IC draws a maximum of ICC from the supply voltage source. The device will initiate another soft start sequence in the event of a shutdown due to a fault, which activates the protection circuitry, or if the supply voltage drops below the UVLO turn off threshold of VCC UVLO.
Standby Mode
The IC is in this state if the supply voltage has exceeded VCC ON and the VFB pin voltage is less than 20% of VREF . The oscillator is running and all internal circuitry is biased in this state but the gate is inactive. This state is accessible from any other state of operation except OVP. The IC enters this state whenever the VFB pin voltage has decreased to 50% of VREF when operating in normal mode or during a peak current limit fault condition, or 20% VREF when operating in soft start mode.
Fault Protection Mode
The fault mode will be activated when any of the protection circuits are activated. The IC protection circuits include Supply Voltage Under Voltage Lockout (UVLO), Output Over Voltage Protection (OVP), Open Loop Protection (OLP), Output Undervoltage Protection (OUV), and Peak Current Limit Protection (IPK LIMIT).
Sleep Mode
The sleep mode is initiated by pulling the OVP pin below 0.62V (typ). In this mode the IC draws a very low quiescent supply current.
Soft Start Mode
This state is activated once the VCC voltage has exceeded V CCON and the V FB pin voltage has exceeded 20% of VREF. The soft start time, which is defined as the time required for the duty cycle to linearly increase from zero to maximum, is dependent upon the values selected for compensation of the voltage loop pin COMP to pin COM. Throughout the soft start cycle, the output of the voltage error amplifier (pin COMP) charges through the compensation network. This forces a linear rise of the voltage at this node which in turn forces a linear increase in the gate drive duty cycle from 0. This controlled duty cycle reduces system component stress during start up conditions as the input current amplitude is increasing linearly.
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IR1150S/IR1150IS(PbF)
AC POWER ON
Gate Inactive Oscillator Inactive
STATE & TRANSITIONS DIAGRAM
VCC < VCCon Gate Inactive Oscillator Inactive I CC MAX = 200uA VCC > VCCon
UVLO
Sleep
VOVP <0.7V Gate Inactive Oscillator Inactive I CC max = 200uA
VCC < VCC UVLO
STAND- BY
VFB < 20% VREF Gate Inactive Oscillator Active I CC MAX = 4mA VFB > 20%VREF
VOVP >0.7V VOVP <0.7V
VFB < 50%V REF
V CC < VCC UVLO
VFB < 20% V REF V CC < VCC UVLO VISNS < -1.0V VISNS > -1.0V VFB < 80% V REF Gate Active Oscillator Active Pulse Width Increasing 0- 97 % Duty Cycle VFB > 80%VREF
I PK LIMIT
VISNS < -1.0V Present PulseTerminated Oscillator Active
SOFT START
VOVP <0.7V
FAULT
V CC < VCC UVLO VISNS < -1.0V VISNS > -1.0V Gate Active Oscillator Active I CC MAX = 28 mA
NORMAL
VFB < 50%V REF
VOVP <0.7V
VOVP < 101% VREF VOVP > 105%VREF
OVP FAULT
VOVP > 105%VREF Gate Inactive Oscillator Active
VOVP <0.7V
V CC < VCC UVLO
VOVP <0.7V
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IR1150S/IR1150IS(PbF)
100
13 V
VCC UVLO Thresholds VCC UVLO Thresholds
10 ISUPPLY
12 V
1
11 V
0.1
10 V
VCC ON VCC ON VCC UVLO VCC UVLO
0.01 5V 10 V 15 V 20 V Supply voltage 25 V
9V -50 C
0 C
50 C 100 C Temperature
150 C
Fig.1 - Supply Current
Fig. 2 - Under Voltage Lockout vs. Temperature
300 kHz Switching Frequency (typ.) - f SW 250 kHz Switching Frequency 200 kHz 150 kHz 100 kHz 50 kHz 0 kHz 0k 50 k 100 k 150 k 200 k Programming Resistor
250 kHz
200 kHz
RF RF=37k RF RF=78k RF RF=165k
150 kHz
100 kHz
50 kHz
0 kHz -50 C 0 C 50 C 100 C Temperature 150 C
Fig. 3 - Oscillator Frequency vs. Programming Resistor
Fig. 4 - Oscillator Frequency vs. Temperature
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IR1150S/IR1150IS(PbF)
7.10 V EA Transconductance (typ.) - g m 0 C 50 C 100 C Temperature 150 C
50 uS
Reference Voltage (typ.) - VREF
7.05 V
45 uS
7.00 V
40 uS
6.95 V
6.90 V
35 uS
6.85 V -50 C
30 uS -50 C 0 C 50 C 100 C Temperature 150 C
Fig. 5 - Reference Voltage
Fig. 6 - Voltage Error Amplifier Transconductance
60 uA Error Amplifier Current Source/Sink
2.70
50 uA Current Sense DC Gain 150 C
2.60
40 uA
2.50
30 uA
IO (source) IO (sink)
20 uA
2.40
10 uA -50 C 0 C 50 C 100 C Temperature
2.30 -50 C 0 C 50 C 100 C Temperature 150 C
Fig.7 - Voltage Error Amplifier Source/Sink Current
Fig. 8 - Current Sense Amplifier DC Gain
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IR1150S/IR1150IS(PbF)
IR1150 Timing Diagrams
Vcc
IC Supply Voltage (VCC )
13.0V (typ)
11.0V (typ)
t
UVLO NORMAL UVLO
Vcc Under Voltage Lockout
106% VREF 100% VREF 82% VREF
Feedback Voltage (VFB)
51% VREF 19% VREF
t
OLP SOFT START OVP NORMAL OUV OLP
Output Protection
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IR1150S/IR1150IS(PbF)
Case outline
D A 5 B
FOOTPRINT 8X 0.72 [.028]
DIM A b c D
INCHES MIN .0532 .013 .0075 .189 .1497 MAX .0688 .0098 .020 .0098 .1968 .1574
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00
A1 .0040
6 E
8
7
6
5 H 0.25 [.010] A
E
6.46 [.255]
1
2
3
4
e e1 H K
.050 BASIC .025 BASIC .2284 .0099 .016 0 .2440 .0196 .050 8
1.27 BASIC 0.635 BASIC 5.80 0.25 0.40 0 6.20 0.50 1.27 8
6X
e e1
3X 1.27 [.050]
L
8X 1.78 [.070]
y
A C 0.10 [.004] y
K x 45
8X b 0.25 [.010]
A1 CAB
8X L 7
8X c
NOTES: 1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994. 2. CONTROLLING DIMENSION: MILLIMETER 3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INC HES]. 4. OUTLINE CONFORMS TO JEDEC OUTLINE MS-012AA.
5 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006]. 6 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010]. 7 DIMENSION IS THE LENG TH OF LEAD FOR SOLDERING TO A SUBSTRATE.
8-Lead SOIC
01-6027 01-0021 11 (MS-012AA)
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IR1150S/IR1150IS(PbF)
Tape & Reel Information
Dimensions are shown in millimeters (inches)
TERMINAL NUMBER 1
12.3 ( .484 ) 11.7 ( .461 )
8.1 ( .318 ) 7.9 ( .312 )
FEED DIRECTION
NOTES: 1. OUTLINE CONFORMS TO EIA-481 & EIA-541. 2. CONTROLLING DIMENSION : MILLIMETER.
330.00 (12.992) MAX.
14.40 ( .566 ) 12.40 ( .488 ) NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
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IR1150S/IR1150IS(PbF)
PART MARKING INFORMATION
?
? P
()
MARKING CODE Lead Free Released Non-Lead Free Released
LOT CODE
ORDER INFORMATION
Basic Part 8-Lead SOIC IR1150STR order IR1150STR 8-Lead SOIC IR1150ISTR order IR1150ISTR Lead-free Part 8-Lead SOIC IR1150S order IR1150STRPbF 8-Lead SOIC IR1150ISTR order IR1150ISTRPbF
The IR1150S(PbF) has been designed and qualified for the Consumer Market The IR1150IS(PbF) has been designed and qualified for the Industrial Market Qualification Standards can be found on IR's Web site. WORLD HEADQUARTERS: 233 Kansas Street, El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. 6/13/2005
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